The present invention relates to dividers, and more particularly to a programmable non-integer fractional divider.
Phase-locked loops (PLLs) are used in a wide variety of applications in semiconductor devices. For example, PLLs are used in clock generators, frequency multipliers, frequency synthesizers, servo systems in disk drives and more recently in wireless networks. Naturally, in all of these and other applications the accuracy and reliability of the PLL is of critical importance.
A common phase-locked loop comprises a phase comparator, a charge pump, a filter, a voltage-controlled oscillator (VCO) and a feedback divider. The general operation of PLL""s is well known, so only a brief explanation will be given. The phase comparator compares a reference input signal xe2x80x98Fqxe2x80x99 from a quartz to a feedback signal from the feedback divider. Depending upon the phase difference between the input signal and feedback signal, the phase comparator drives the charge pump. The output of the charge pump is filtered by the filter, and is used to drive the VCO. The VCO comprises a voltage-to-current converter and a current controlled oscillator. Thus, the VCO receives a voltage at its input and outputs a signal with a frequency proportional to that signal. Of course, those skilled in the art will recognize that this description of the VCO is essentially arbitrary and that the VCO could be illustrated as separate voltage-to-current converter and current-controlled oscillator rather than as a single element. The output of VCO fed back through feedback divider to phase comparator. The feedback divider divides down the VCO output signal frequency xe2x80x98Fvcoxe2x80x99 to match the quartz input signal frequency xe2x80x98Fqxe2x80x99 so they can be phase compared.
The frequency at which the phase-locked loop operates is dependent upon the frequency of the VCO and the amount of division by the feedback divider. To change the VCO output frequency xe2x80x98Fvcoxe2x80x99, these elements must be adjusted. Typically, the frequency at the input of the feedback divider xe2x80x98Fvcoxe2x80x99 is divided by an integer ratio xe2x80x98Nxe2x80x99 in the way that             F      out        =                  F        vco            N        ,
where N is the integer value.
In some circuits, to improve the granularity of the system the quartz input signal frequency xe2x80x98Fqxe2x80x99 is also divided by an integer ratio xe2x80x98Bxe2x80x99 before entering the phase comparator. The two frequencies at the input of the comparator are then related according to the formula:             F      vco        N    =      Fq    B  
which may be rewritten as:   Fvco  =      Fq    xc3x97          N      B      
It is readily understood that a high granularity may be obtained by increasing the value of xe2x80x98Bxe2x80x99.
Unfortunately the higher the value of xe2x80x98Bxe2x80x99 is, the lower the PLL bandwidth xe2x80x98BWpllxe2x80x99 is, according to the formula:   Bwpll  =            Fq      ÷      10        xc3x97          1      B      
Therefore, with the known integer dividers, a tradeoff is to be found between granularity and PLL bandwidth values.
One obvious solution to have a high PLL bandwidth is to have a value of xe2x80x98Bxe2x80x99 equal to xe2x80x981xe2x80x99, but in such case the granularity is limited to the value of Fq.
Non-integer values for xe2x80x98Nxe2x80x99 are a solution for reducing the incremental performance granularity normally taken for integer ratios.
Such a prior art circuit for producing a non-integer ratio is disclosed in U.S. Pat. No. 4,891,774 from Bradley in which a dual modulus fractional divider having a dual modulus prescaler is coupled to a programmable divider. Latches and a full adder are provided for programming the programming divider with a modulus A, a modulus B, a modulus (Axe2x88x921) and a modulus (B+1). A rate multiplier controls the adder to provide the desired resolution of the divider.
However, those existing circuits for producing non-integer ratios are limited to a few non-integer values.
Thus, the prior art PLL designs only allow the users to trade-off between xe2x80x98a high granularity with a narrow bandwidthxe2x80x99 or xe2x80x98a wide bandwidth with a weak granularityxe2x80x99.
U.S. application Ser. No. 09/693057 from the assignee, discloses a programmable non-integer fractional divider which uses the xe2x80x98Nxe2x80x99 internal phases of the VCO as inputs, and delivers an output xe2x80x98Fdivxe2x80x99 whose frequency is a non integer sub-multiple of the VCO frequency xe2x80x98Fvcoxe2x80x99. This solution is well suited for an implementation based on a high level language description. Unfortunately, the use of a high level language to implement and synthesize the different logic blocks of this programmable non-integer fractional divider is not well suited when high frequency performance and high timing accuracy are required. This programmable non-integer fractional divider is able to operate at a maximum frequency of 300 MHz under worst case conditions of a 0.25 xcexcm CMOS technology.
Moreover, this programmable fractional divider is designed to delivered a 50% duty cycle. This feature is obtained by the use of an xe2x80x98even and oddxe2x80x99 integer counter and an xe2x80x98even and oddxe2x80x99 non-integer incrementer.
However, in some PLL applications the need to get a divided frequency with a 50% duty cycle to feed the phase frequency detector (PFD) is not mandatory. Indeed, all the PFD""s work on one edge (either the rising or the falling edge) and do not care of the opposite one (respectively the falling or rising one). Consequently, the PFD""s do not required a 50% duty cycle.
Therefore, there exist a need to provide an improved PLL that can operate on a wide bandwidth while having a high granularity, and that can operate on various duty cycles.
The present invention solves the foregoing need by using a VCO generating a plurality of out-of-phase clock signals coupled to a non-integer fractional divider. According to the present invention, the fractional divider comprises means for dividing a reference clock signal xe2x80x98Fvcoxe2x80x99 having a period xe2x80x98Pxe2x80x99 by a non-integer ratio xe2x80x98Kxe2x80x99. In a preferred embodiment, the divider comprises means for receiving a plurality xe2x80x98Nxe2x80x99 of clock signals xe2x80x98Fvcoxe2x80x940 to Fvco_(nxe2x88x921)xe2x80x99 issued from the reference clock signal xe2x80x98Fvcoxe2x80x99, and wherein each clock signal is equally phase shifted by a xe2x80x98P/Nxe2x80x99 delay one over the other. Selection means are coupled to the receiving means for selecting a first and a second clock signals between the plurality xe2x80x98Nxe2x80x99 of clock signals xe2x80x98Fvcoxe2x80x940 to Fvco_(nxe2x88x921)xe2x80x99. The selected clock signals are such that the phase shift delay between the two selected clock signals is representative of the non-integer value of the ratio xe2x80x98Kxe2x80x99. The selected clock signals are combined into combining means responsive to the receiving means to output a divided clock signal xe2x80x98Fvco/Kxe2x80x99. The appropriate selection of the first and second clock signals is repeated at each clock cycle according to a general formula wherein xe2x80x98Kxe2x80x99 is the summation of an integer I, and a decimal X values:
K=I+X
The output duty cycle is equal to:   Duty_cycle  =      1    K  
In a preferred embodiment, the circuits are full custom design in order to get a very high frequency performance. As a result, in operation the fractional divider of the present invention exhibits a xc3x973 performance improvement compared to previous approach which means an operating frequency of 900 MHz under worst case conditions of a 0.25 xcexcm CMOS technology.
In application, the invention is suitable to operate on a bandwidth range of hundred of MHz with a granularity of hundred of kHz.
The non-integer fractional divider of the present invention thus enables:
i) a drastically simplification of the overall design, and
ii) a drastically improvement of the maximum frequency of operation as compared to the prior art solutions by providing:
a circuitry which reduces the total number of devices used; and
a new state machine algorithm which simplifies the control logic circuit.
Preferably, the system of the invention is a non-integer fractional divider for dividing a reference clock signal xe2x80x98Fvcoxe2x80x99 of period xe2x80x98Pxe2x80x99 by a non-integer ratio xe2x80x98Kxe2x80x99, the non-integer ratio being decomposed into an integer part xe2x80x98Ixe2x80x99 and a non-integer part xe2x80x98Xxe2x80x99. The non-integer fractional divider comprising:
first and second receiving means for respectively receiving an identical plurality xe2x80x98Nxe2x80x99 of clock signals xe2x80x98Fvcoxe2x80x940 to Fvco_(Nxe2x88x921)xe2x80x99, each clock signal having a period of xe2x80x98Pxe2x80x99 and being equally phase shifted by a xe2x80x98P/Nxe2x80x99 delay one over the other and wherein the first clock signal xe2x80x98Fvcoxe2x80x940xe2x80x99 being in phase with the reference clock signal;
means coupled to the first and second receiving means for selecting a first clock signal xe2x80x98PHI1xe2x80x99 from the first receiving means and a second clock signal xe2x80x98PHI2xe2x80x99 from the second receiving means;
means for detecting the end of a (Ixe2x88x92i)th period, wherein xe2x80x98ixe2x80x99 is a predetermined value;
means coupled to the first and second receiving means and to the detection means for combining said first and second selected clock signals (PHI1, PHI2) to generate a clock signal xe2x80x98Clockxe2x80x99 being phase shifted by the non-integer part value xe2x80x98Xxe2x80x99 of the non-integer ratio; and
means (205) coupled to the combining means (204) for dividing the shifted clock signal by the integer part xe2x80x98Ixe2x80x99 of the non-integer ratio.